1. Field of the Invention.
The invention relates to the field of semiconductor memories, more particularly to read-only memories.
2. Prior Art.
The present invention is directed to a read-only memory (ROM), more particularly to a memory used with a microprocessor where the microprocessor time-multiplexes addresses and data on a bus. One commercial embodiment of a system where the address/data lines are shared is in the Intel Multibus. Typically in these systems, address signals are latched in an external latch for use by circuits operating with the microprocessor such as RAM, ROM, I/O, ports, peripherals, etc. A more thorough discussion of the prior art as it relates to these microprocessor is described in conjunction with FIG. 1.
In the present invention, latches are incorporated within a ROM for storing address signals. The address signals are made available from the latch to other circuits operating with the microprocessors. Latches have been incorporated in memories including EPROMs, however, for different purposes.
In U.S. Pat. No. 4,545,038 (column 1, line 45 to column 2, line 15) a latch is described which stores data used for the programming of an electrically programmable read-only memory (EPROM). Other patents describing latches are U.S. Pat. Nos. 4,587,637, 4,610,004, 4,646,269, 4,691,298, 4,715,017, 4,725,945 and 4,460,982.
There are commercially available EPROMs which store address signals in internal latches, however, the addresses are only used for internal purposes. Products known to Applicant which employ these latches are Intel Part Nos. 87C257 and 87C64.